In processes of fabricating microelectronic devices, multiple layers of conducting, semiconducting, and dielectric materials are deposited onto a surface of a substrate in a stepwise fashion. Portions of the layers may be removed, followed by further processing by selectively adding and removing materials, all with great precision. As layers are deposited onto or removed (e.g., by etching) from the substrate, the uppermost surface of the substrate may become non-planar. Before adding more material, the non-planar surface is sometimes processed by “planarization” to produce a smooth surface for a subsequent layer and processing.
Planarizing or polishing a non-planar surface is a process where material of a non-planar surface is removed to leave a highly planar surface. Planarization is useful to remove undesired surface topography such as a rough (un-even) surface, or defects such as agglomerated materials, crystal lattice damage, scratches, or contaminated layers or materials. In certain uses, planarization removes excess material that has been deposited over a substrate surface to fill features such as channels or holes of a lower layer or layers.
Chemical-mechanical planarization, or chemical-mechanical polishing (CMP), is an established commercial technique for planarizing substrates in microdevice fabrication. CMP uses a liquid chemical composition known as a “CMP composition,” alternately a “CMP slurry,” or just “slurry,” in combination with a CMP pad, to mechanically and chemically remove material from a substrate surface. A slurry can be applied to a substrate by contacting the surface of the substrate with a CMP polishing pad to which the slurry has been applied. Material is typically removed from the substrate surface by a combination of mechanical activity of abrasive material contained in the slurry, and chemical activity of chemical materials of the slurry.
To continue reducing sizes of microelectronic devices, components that make up devices must be smaller and must be positioned ever more closely together. Electrical isolation between circuits is important for ensuring peak semiconductor performance, but becomes increasingly difficult with smaller devices. To that end, various fabrication methods involve etching shallow trenches into a semiconductor substrate and then filling the trenches with insulating (dielectric) material, thereby isolating nearby active regions of an integrated circuit. One example of such a process is referred to as shallow trench isolation (STI). This is a process in which a semiconductor layer is formed on a substrate, shallow trenches are formed in the semiconductor layer via etching or photolithography, and dielectric material is deposited over the etched surface to fill the trenches.
To ensure complete filling of the trenches, an excess amount of the dielectric material is deposited over the etched surface. The deposited dielectric material (e.g., a silicon oxide) conforms to the topography of the underlying semiconductor substrate, including at the trenches. Thus, after the dielectric material has been placed, the surface of the deposited dielectric material is characterized by an uneven combination of raised areas of the dielectric material separated by trenches in the dielectric material, the raised areas and trenches corresponding to raised areas and trenches of the underlying surface. The region of the substrate surface that includes the raised dielectric material and trenches is referred to as a “pattern” field of the substrate or the “active” field, e.g., as “pattern material,” “pattern oxide,” “pattern dielectric,” “active oxide,” etc. This region is characterized by a “step height,” which is the difference in height of the raised areas of the dielectric material relative to the trench height. Excess dielectric material that makes up the raised areas is removed by a CMP process to produce a planar surface.
Chemical mechanical processing for removing pattern dielectric materials can be characterized by performance parameters that include various removal rates, “trench loss,” and “planarization efficiency.”
A removal rate is a rate of removal of material from a surface of a substrate, usually expressed in terms of units of length (thickness) per unit of time (e.g., Angstroms (Å) per minute). Different removal rates relating to different regions of a substrate or to different stages of a removal step can be important in assessing process performance. A “pattern removal rate” (alternately “active” removal rate) is the rate of removal of material from a desired (“active” or “target”) area of a substrate, such as removal of dielectric material from raised areas of pattern dielectric at a stage of a process during which a substrate exhibits a substantial step height. “Blanket removal rate” refers to a rate of removal of dielectric material from a planarized (i.e., “blanket”) dielectric material at an end of a polishing step, when step height has been significantly (e.g., essentially entirely) reduced.
In addition to a high active removal rate, another performance factor that is important in processing a dielectric substrate is planarization efficiency (PE), which is related to “trench loss.” During removal of raised area dielectric material, an amount of material of trenches will also be removed. This removal of material from trenches is referred to as “trench loss.” In a useful CMP process, the rate of removal of material from trenches is well below the rate of removal from raised areas. Thus, as material of the raised areas is removed (at a faster rate compared to material being removed from the trenches) the pattern dielectric becomes a planarized surface that may be referred to as a “blanket” region of the processed substrate surface, e.g., “blanket dielectric” or “blanket oxide.” Trench loss is the amount (thickness, e.g., in Angstroms (Å)) of material removed from trenches in achieving planarization of pattern material by eliminating an initial step height. Trench loss is calculated as the initial trench thickness minus a final trench thickness. Planarization efficiency relates to the amount of step height reduction achieved per amount of trench loss that occurs, while getting to a planar surface, i.e., step height reduction divided by trench loss.
Various chemical ingredients may be used in a CMP composition to improve or control trench loss, planarization efficiency, and removal rates. Certain chemical compounds have been used on slurries to control trench loss, e.g., by controlling a removal rates; these are sometimes referred to as “inhibitors.” But these inhibitors can also have the effect of reducing an active removal rate, among other potentially detrimental effects. In attempts to improve planarization efficiency, an added chemical ingredient is useful only if it does not also produce a different and overriding negative effect on the slurry or CMP process, such as instability of the slurry, an increase in defects in a processed substrate, or a substantial reduction in active removal rate.
In various dielectric polishing steps (e.g., during STI processing or when processing a NAND or 3D-NAND substrate) the rate of removal of pattern dielectric is a rate-limiting factor of the overall process. Therefore, high removal rates of pattern dielectric are needed. Also highly desired is high planarization efficiency, but only if this can be achieved without a substantial decrease in the active removal rate.